Author: Unknown
Subject: Bandwidth of RAM
Date: Sunday, 22 Nov 2020, 21:27:21

I just wanted to check my understanding of this concept. The memory bandwidth of a processor is how much memory it can write/read to a specific part of the memory heiarchy correct?

If so then, we would expect the bandwidth to RAM to be lower than say bandwidth of cache?

Also, how can you have multiple memory references per clock cycle? I thought a clock cycle was exactly measured by making memory references, and therefore, clock rate measured how many mem refs you could make a second?