Author: Stan Eisenstat
Subject: Re: [Cs323] conflict miss
Date: Sunday, 11 Oct 2020, 09:17:49

    > Message Posted By: Unknown
    >
    > When would two blocks want to be in the same line in a conflict miss as
    > defined in the notes? Isn't only one block being read/written at a time
    > from/into the cache?

Consider a direct-mapped cache where the int arrays A[4]
and B[4] are in blocks that map to the same line.  When
the code sequence

  t = A[0]+B[0]; t += A[1]+B[1]; t += A[2]+B[2]; t += A[3]+B[3];

is executed,

  * fetching A[0] is a compulsory miss
  * fetching B[0] is a compulsory miss
  * fetching A[1] is a conflict miss (the A block replaces the B block)
  * fetching B[1] is a conflict miss (the B block 1eplaces the A block)
  ...

Thus there are  8 misses, 6 of which are conflict misses.

--Stan-