Author: Stan Eisenstat
Subject: Re: [Cs323] conflict miss follow-up
Date: Sunday, 11 Oct 2020, 13:03:41

    > Message Posted By: Unknown
    >
    > In the example you gave with A[4] and B[4], how do you know that B was
    > never in the cache when you read B[0], as opposed to B[1]? Also, is the
    > 1-4 supposed to be the offset, or four separate blocks that map into the
    > same line?

The example was:

  Consider a direct-mapped cache where the int arrays A[4]
  and B[4] are in blocks that map to the same line.  When
  the code sequence
   
    t = A[0]+B[0]; t += A[1]+B[1]; t += A[2]+B[2]; t += A[3]+B[3];
   
  is executed,
   
    * fetching A[0] is a compulsory miss
    * fetching B[0] is a compulsory miss
    * fetching A[1] is a conflict miss (the A block replaces the B block)
    * fetching B[1] is a conflict miss (the B block 1eplaces the A block)
    ...
   
  Thus there are  8 misses, 6 of which are conflict misses.

If block A were in the cache when A[0] was fetched, then
there would not have been a miss.  If block B were, then
fetching A[0] would have replaced it by block A and the
fetch of B[0] would have been a conflict miss.

--Stan-