Author: Stan Eisenstat
Subject: Re: [Cs323] Bandwidth of RAM
Date: Tuesday, 24 Nov 2020, 10:37:47
> Message Posted By: Unknown > > I just wanted to check my understanding of this concept. The memory > bandwidth of a processor is how much memory it can write/read to a > specific part of the memory heiarchy correct? The bandwidth of memory is the rate at which one can read/write it. The latency is how long it takes to read/write one byte. ===== > If so then, we would expect the bandwidth to RAM to be lower than say > bandwidth of cache? The latency of a cache is lower than that of RAM. ===== > Also, how can you have multiple memory references per clock cycle? I > thought a clock cycle was exactly measured by making memory references, > and therefore, clock rate measured how many mem refs you could make a second? A clock cycle is is a time unit. Whether one or more memory references may be initiated per cycle depends on the architecture of the memory unit, as does the number of cycles it requires. --Stan-PREV INDEX NEXT